Sundance SMT8081 - Manual (Page 13)

Version 1.0 Page 13 of 13 SMT8081 User Manual
“RSL – Loop-Back”
This command requires and RSL loop-back (i.e. connect RSLA (J5) to RSLB (J3)
using an
SMT522-RSL10 ). It gets the SMT381-VP to generate a sinewave pattern on
each RSL. As RSL connections are full duplex, patterns are received on the other
side and routed to the DAC.
“FPGA - Sinewave Pattern - LOOKUPTABLE mode”
This command sets up the module so the FPGA generates samples coming from a
ROM block (sinewave made of 32 samples) and fed to the DAC via the LVDS bus. It
involves that clock source and frequency have been defined (a DCM reset might be
needed as well).
“DAC - Sinewave Generator - Dac Internal Memory Mode”
This command sets up the module so the DAC is loaded with a sinewave pattern into
its internal Memory. Added to that the on-board VCO is setup to clock the DAC at
500MHz, to reach 1GSPS.
What is provided in the SMT8081 system?
When purchasing an SMT8081 system, you will get the following (unless stated on
order/invoice):
- SMT395-VP30-6 ,
- SMT310Q ,
- SMT381-VP30-6 ( SMT338-VP30-6 and SMT381 ),
- One FMS cable (SMT502),
- SMT516 (SHB PCB),
- SMT511-320 (SHB Cable 320mm long),
- SMT520-06 (MMBX to BNC cables),
- SMT522-RSL10 (RSL flexi cable – 10 inches long).