Sundance SMT8081 - Manual (Page 12)

Version 1.0 Page 12 of 13 SMT8081 User Manual
“FPGA CONFIG - Configure FPGA - for sending bitstream”
This command loads a bitstream (smt381_vp.bit – located in the same directory as
the 3L application). It can be used straight after power-up or after an ‘FPGA CONFIG
- Pull INIT low - for reconfiguration (new bitstream)’ when loading a new/different
bitstream.
“FPGA CONFIG - Retrieve configuration - FPGA already configured”
This command is used once the FPGA has already been configured and a reset has
occurred. It sends an ‘END KEY’ (please refer to SMT338-VP User Guide) to retrieve
the FPGA configuration previously loaded.
“RESET - DAC - all DAC internal registers”
This command resets all DAC internal registers to their default value.
“RESET – FPGA - Reset FPGA DCM”
This command sends a control word to the FPGA to reset its DCM. This is to be done
when the sampling frequency is changed. In that case, it is likely for the DCM to
unlock. Resetting it forces it to re-lock.
“SETTINGS - Select DAC Clock Source”
This command prompts for a value, selecting either sources: on-board Clock
Synthesizer, on-board VCO or external Clock.
“SETTINGS - Clock Synthesizer Frequency Setting”
This command prompts for a value in MHz for setting the on-board Clock
Synthesizer. The value entered should be within the range 60-420 MHz. This is a
DDR clock frequency. The maximum (420 MHz – due to the FPGA DCM limitation)
allows to the DAC to sampling at 840 MSPS.
“SETTINGS - VCO Frequency Setting”
This command prompts for a value in MHz for setting the on-board VCO.
“SHB – using DPRAM Data Source - SHBTODPRAM mode”
This command prompts for a sampling frequency (on-board Clock Synthesizer), sets
up clock source and frequency, loads an FPGA internal FIFO via SHB buses and
reads samples out continuously.
“SHB - Direct Data Source - SHBDIRECTODAC mode”
This command prompts for a sampling frequency (on-board Clock Synthesizer), sets
up clock source and frequency, and launches 2 threads that output continuously
samples to the DAC via SHB buses and through the LVDS bus.