ATI Audio DDA124-BNC - Manual (Page 3)

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DESCRIPTION
INPUTS
Incoming AES/EBU formatted digital audio data is applied to input transformers
T8 (T9 for second input channel of dual unit). Both XLR and BNC inputs are
balanced and DC isolated from ground. Input blocking capacitors C22 (C24)
prevent accidental DC inputs from saturating (and perhaps damaging) the input
transformers. Input termination resistors R25 (R26) at 75 ohms for BNC (and
SP/DIF) inputs or 110 ohms for XLR inputs can be switched in or out of the circuit
with rear panel DIP switches S1a (S1b). Inputs should always be terminated
unless they are looped thru to another device or DDA input. The last device or
input should always terminate the line.
INPUT EQUALIZERS
The input signals feed cable equalizer circuits U3 (U4) and associated
components. Input equalization should only be necessary for extremely long
input cable lengths and should only be used if proven to be necessary. The
equalizers are adjustable with front panel multi-turn trimpots R63 (R66) so that
only the minimum amount of boost required to compensate for excess cable roll-
off can be added without over-equalization, which can degrade noise margins.
See adjustment instructions in the INSTALLATION section. If input equalization
is not required and you want to protect yourself from random control diddlers, you
may disable the equalizers by removing jumpers E4 (E5).
RECEIVERS
(Note that DSA Series units do not re-clock and provide no front panel status
information. The following section applies to DDA Series units only.)
The equalized AES/EBU data stream is applied to the receiver circuit U8 (U17)
that is a Crystal Semiconductor CS8414 96kHz Digital Audio Receiver IC. The
CS8414 receives the data, recovers the clock and synchronization signals and
separates the audio and digital data. The audio data may be 16 to 24 bits at
sample rates from 27 to 96 kHz.
Frame sync (FSYNC), Serial Clock (SCK), Serial audio data (SDATA), Channel
status (C), User channel data (U), and data validity information (VERF) are
passed directly to the transmitter IC for reformatting into the output data stream.
VERF is an OR’ing of the validity information from the incoming data (V) with an
internal error flag (ERF) that detects serious transmission errors such as parity
errors, bi-phase coding violations and an out-of-lock PLL receiver. VERF then
becomes the transmitted validity bit (V) and can be used by downstream error
correction devices to interpolate through errors.
Received frequency information is encoded on U8 (U17) pins F0, F1 and F2 and
is decoded by U14 (U19) into two BCD digits for display. Error information is
encoded on pins E0, E1 and E2. It is decoded by 3 to 8 line decoder U20 (U22)
and sent to the front panel display LEDs.