Zilog Z8F0880 - Manual (Page 9)

Z8 Encore! XP
®
Dual F1680 Series Development Kit
User Manual
UM021204-0508 Z8 Encore! XP
®
Dual F1680 Series
6
•
RS-232 interface.
•
Two MDS connectors.
•
I
2
C-driven DAC that provides analog input for the Z8F1680_S
device.
•
The Slave device has a 20 MHz crystal; the Master device uses
internal IPO.
•
On-chip debugger interface.
The module has two main modes of operation:
•
Downloading and debugging code into the Slave device through the
Master device, using the connection of the OCD of the Slave device
to the UART1 of the Master device. In this case, PA7 of the Master
device is acting as a Reset source for the Slave device and needs to be
configured as an output with Open Drain.
•
Downloading and debugging code in either the Master or Slave
device using the standard OCD interface on either chip.
The operation mode is selected by switch S2.
All the GPIOs of both devices, except for those used on the module are
connected to JP1 and JP2. All the GPIOs of the Slave device, except
analog inputs are connected to the odd pins of JP1. The GPIOs of the
Master device are connected to the even pins of JP1 and to JP2. All the
analog inputs of the Slave device are connected to JP2. Input PB3/ANA3
of the Slave device can be connected through J1 to either the output of U2
(12-bit DAC) or to JP2 pin 6.
The 12-bit DAC7571 manufactured by TI (U2) is controlled either by
Master or Slave device.