American Dynamics PMC-4U-CACI - Manual (Page 21)

Hardware and Software Design • Manufacturing Services
P a g e 21
PMC4U_IRUPT/PMC4U_IRUPT_CLR
[0XE0] PMC-4U Interrupt Latch read status/write clear
INTERRUPT STATUS
DATA BIT DESCRIPTION
4 SCC interrupt
3 UART D interrupt
2 UART C interrupt
1 UART B interrupt
0 UART A interrupt
FIGURE 9 PMC-4U INTERRUPT STATUS/CLEAR
The bits in this register indicate that an interrupt has been received from
the corresponding device. These bits are latched and once set will remain
set until a one is written to the bit to be cleared.