Sony PCV-R558DS - Manual (Page 92)

VAIO Digital Studio™ Reference Manual 78
Chip Configuration Sub-Menu
SDRAM Configuration [By SPD]
User Define
7ns (143MHz)
8ns (125MHz)
SDRAM CAS Latency [3T]
SDRAM RAS to CAS Delay [3T]
SDRAM RAS Precharge Time [3T]
SDRAM Cycle Time (Tras, Trc) [6T, 8T]
5T, 7T
SDRAM Page Closing Policy [All Banks]
One Bank
CPU Latency Timer [Enabled]
Disabled
CPC [Enabled]
Disabled
Graphics [64MB]
32MB
Video Memory Cache Mode [UC]
USWC
AGP 4X Support [Enabled]
Disabled
Memory Hole At 15M-16M [Disabled]
Enabled
PCI 2.1 Support [Enabled]
Disabled
High Priority PCI Mode [Enabled]
Disabled
Onboard PCI IDE Enable [Both]
Primary
Secondary
Disabled