Asus P5L-MX - Manual (Page 69)

ASUS P5L-MX 2-23
2.4.4 Chipset
The Chipset menu allows you to change the advanced chipset settings.
Select an item then press to display the sub-menu.
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
The following sub-items appear when this item is Disabled.
Configuration options: [Disabled] [Enabled]
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available.
Configuration options: [6 Clocks] [5 Clocks] [4 Clocks] [3 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]
[5 Clocks] [6 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and
the read/write command. Configuration options: [2 Clocks] [3 Clocks]
[4 Clocks] [5 Clocks] [6 Clocks]
DRAM RAS# Activate to Precharge [15 Clocks]
Sets the RAS Activate timing to Precharge timing.
Configuration options: [4 Clock] [5 Clocks] ~ [18 Clocks]
Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
Select Screen
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
Advanced Chipset Settings
Configure DRAM Timing by SPD [Enabled]
Hyper Path 3 [Auto]
DRAM Throttling Threshold [Auto]
Booting Graphic Adapter Priori [PCI Express/Int-VG]
Internal Graphics Mode Select [Enabled, 8MB]
Graphics memory type [Auto]
Boot Display Device [Auto]
Flat Panel Type [Type 1]
Local Flat Panel Scaling [Auto]
TV Connector [Auto]
HDTV Output [Auto]
TV Standard [VBIOS-Default]
PEG Buffer Length [Auto]
Link Latency [Auto]
PEG Root Control [Auto]
Slot Power [Auto]
High Priority Port Select [Disabled]