AMD ATHLON K - Manual (Page 5)

5
23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide
Preliminary Information
1 Product Errata
This section documents AMD Athlon processor model 4 product errata. The errata are divided into
categories to assist referencing particular errata. A unique tracking number for each erratum has been
assigned within this document for user convenience in tracking the errata within specific revision
levels. Table 1 cross-references the revisions of the processor to each erratum. An “X” indicates that
the erratum applies to the stepping. The absence of an “X” indicates that the erratum does not apply
to the stepping. Shading within the table indicates an addition or modification from the previous
release of this document.
Note: There can be missing errata numbers. Errata that have been resolved from early revisions of the
processor have been deleted, and errata that have been reconsidered may have been deleted or
renumbered.
Table 1. Cross-Reference of Product Revision to Errata
Errata Numbers and Description
Revision Numbers
A4 A5 A6 A7 A9
5 MCA Bus Unit Control Register MSR 408H Returns Incorrect Information X X X X X
10 Resistance Value of the ZN and ZP Pins X X
11 PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation
Circuit to Fail
X X X X X
13 Instruction Execution Deadlock X X X X
14 Processors with Half-Frequency Multipliers May Hang Upon Wake-up from
Disconnect
X X X X X
15 Processor Does Not Support Reliable Microcode Patch Mechanism X
16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with
Certain Linear Addresses
X X X X X
17 Code Modifications that Coincide with Level 2 Instruction TLB Translations
May Escape Detection Resulting in Stale Code Execution
X X X X X
20 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-
Time Stale Execution
X X X X X
21 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation X X X X X
22 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults X X X X X
23 Single Step Across I/O SMI Skips One Debug Trap X X X X X
24 Software Prefetches May Report A Page Fault X X X X X