AMD ATHLON K User Manual
Revision guide, Amd athlon™ processor model 4
Table of contents
Document Outline
- AMD Athlon™ Processor Model 4 Revision Guide
- 1 Product Errata
- Table 1. CrossReference of Product Revision to Errata
- Table 2. CPUID Values for the Revisions of the AMD Athlon™ Processor Model 4
- 5 MCA Bus Unit Control Register MSR 408H Returns Incorrect Information
- 10 Resistance Value of the ZN and ZP Pins
- 11 PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail
- 13 Instruction Execution Deadlock
- 14 Processors with Half-Frequency Multipliers May Hang Upon Wake-up from Disconnect
- 15 Processor Does Not Support Reliable Microcode Patch Mechanism
- 16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain Linear Addre...
- 17 Code Modifications that Coincide with Level 2 Instruction TLB Translations May Escape Detectio...
- 20 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-Time Stale Execution
- 21 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation
- 22 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults
- 23 Single Step Across I/O SMI Skips One Debug Trap
- 24 Software Prefetches May Report A Page Fault
- 2 Revision Determination
- 3 Technical and Documentation Support