AAEON EMB-CV2 - Manual (Page 66)

M i n i - I T X E M B - C V 2
Appendix A Programming the Watchdog Timer A-5
01h: Time-out occurs after 1 second/minute
02h: Time-out occurs after 2 second/minutes
03h: Time-out occurs after 3 second/minutes
…………………………………………………..
FFh: Time-out occurs after 255 second/minutes
CR F7h. (WDTO# Control & Status Register; Default 00h)
BIT READ/WRITE DESCRIPTION
7 R/W
Mouse interrupt reset watch-dog timer enable
0: Watchdog timer is not affected by mouse interrupt.
1: Watchdog timer is reset by mouse interrupt.
6 R/W
Keyboard interrupt reset watch-dog timer enable
0: Watchdog timer is not affected by keyboard interrupt.
1: Watchdog timer is reset by keyboardd interrupt.
5 Write
“1” Only Trigger WDTO# event. This bit is self-clearing.
4
R/W
Write
“0”Clear
WDTO# status bit
0: Watchdog timer is running.
1: Watchdog timer issue time-out event.
3~0 R/W
These bits select IRQ resource for WDTO#. (02h for
SMI# event.)