Electrical characteristics (continued) – Rainbow Electronics MAX1197 User Manual
Page 5
MAX1197
Dual, 8-Bit, 60Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= OV
DD
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k
Ω
resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 60MHz, T
A
= T
MIN
to T
MAX
, unless otherwise
noted.
≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T
A
= +25
°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
T YP
MAX
UNITS
CLK
0.2
×
V
DD
Input Low Threshold
V
IL
PD,
OE, SLEEP, T/B
0.2
×
OV
DD
V
Input Hysteresis
V
HYST
0.15
V
I
IH
V
IH
= V
DD
= OV
DD
±20
Input Leakage
I
IL
V
IL
= 0
±20
µA
Input Capacitance
C
IN
5
pF
DIGITAL OUTPUTS (D7A–D0A, D7B–D0B)
Output Voltage Low
V
OL
I
SINK
= -200
µA
0.2
V
Output Voltage High
V
OH
I
SOURCE
= 200
µA
OV
DD
- 0.2
V
Three-State Leakage Current
I
LEAK
OE = OV
DD
±10
µA
Three-State Output Capacitance
C
OUT
OE = OV
DD
5
pF
POWER REQUIREMENTS
Analog Supply Voltage Range
V
DD
2.7
3
3.6
V
Output Supply Voltage Range
OV
DD
C
L
= 15pF
1.7
3
3.6
V
Operating, f
INA & B
= 20MHz at
-1dB FS applied to both channels
40
50
Sleep mode
3
mA
Analog Supply Current
I
VDD
Shutdown, clock idle, PD =
OE = OV
DD
0.1
20
µA
Operating, f
INA & B
= 20MHz at
-1dB FS applied to both channels (Note 6)
9
mA
Sleep mode
3
Output Supply Current
I
OVDD
Shutdown, clock idle, PD =
OE = OV
DD
3
10
µA
Operating, f
INA & B
= 20MHz at
-1dB FS applied to both channels
120
150
Sleep mode
9
mW
Analog Power Dissipation
PDISS
Shutdown, clock idle, PD =
OE = OV
DD
0.3
60
µW
Offset, V
DD
±5%
±3
Power-Supply
Rejection
PSRR
Gain, V
DD
±5%
±3
mV/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
t
DO
C
L
= 20pF (Notes 1, 7)
6
9
ns
OE Fall to Output Enable Time
t
ENABLE
5
ns
OE Rise to Output Disable Time
t
DISABLE
5
ns
CLK Pulse Width High
t
CH
Clock period: 16.67ns (Note 7)
8.33 ± 1.5
ns
CLK Pulse Width Low
t
CL
Clock period: 16.67ns (Note 7)
8.33 ± 1.5
ns