Rainbow Electronics MAX1139 - Manual (Page 16)

MAX1136–MAX1139
The device memory contains all of the conversion
results when the MAX1136–MAX1139 release SCL. The
converted results are read back in a first-in-first-out
(FIFO) sequence. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF will be
excluded from a multichannel scan. The memory con-
tents can be read continuously. If reading continues
past the result stored in memory, the pointer will wrap
around and point to the first result. Note that only the current conversion results will be read from memory.
The device must be addressed with a read command
to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
16 ______________________________________________________________________________________
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS A
7 1 1
R CLOCK STRETCH
NUMBER OF BITS
P or Sr
1 8
RESULT 8 LSBs
8
RESULT 2 MSBs A A
1
A. SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
7 1 1
R CLOCK STRETCH A
NUMBER OF BITS
P or Sr
1 8
RESULT 1 ( 2MSBs) A
1
A
8
RESULT 1 (8 LSBs) A
8
RESULT N (8LSBs) A
1 8
RESULT N (8MSBs)
SLAVE TO MASTER
MASTER TO SLAVE
CLOCK STRETCH
t ACQ1
t CONV2
t ACQ2
t CONVN
t ACQN
t CONV
t ACQ
1 1
t CONV1
Figure 10. Internal Clock Mode Read Cycles
SLAVE ADDRESS
t CONV1
t ACQ1 t ACQ2
t CONVN
t ACQN
t CONV
t ACQ
NUMBER OF BITS
NUMBER OF BITS
1 8
A
1
S
1
A
7 1 1
R
S
1 7 1 1
R P OR Sr
1 8
A
1
A
8
A
8
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1 1
SLAVE ADDRESS P OR Sr RESULT (8 LSBs)
8
A
1
RESULT (2 MSBs)
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
RESULT 1 (2 MSBs) RESULT 2 (8 LSBs) RESULT N (8 LSBs) A
1 8
RESULT N (2 MSBs) A
Figure 11. External Clock Mode Read Cycle