Rainbow Electronics AT89LS51 - Manual (Page 12)

12
AT89LS51
3053A–8051–05/02
Program
Memory Lock
Bits
The AT89LS51 has three lock bits that can be left unprogrammed (U) or can be programmed
(P) to obtain the additional features listed in the following table.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during
reset. If the device is powered up without a reset, the latch initializes to a random value and
holds that value until reset is activated. The latched value of EA must agree with the current
logic level at that pin in order for the device to function properly.
Programming
the Flash –
Parallel Mode
The AT89LS51 is shipped with the on-chip Flash memory array ready to be programmed. The
programming interface needs a high-voltage (12-volt) program enable signal and is compati-
ble with conventional third-party Flash or EPROM programmers.
The AT89LS51 code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89LS51, the address, data, and control
signals should be set up according to the Flash programming mode table and Figure 4 and
Figure 5. To program the AT89LS51, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/V
PP
to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1
through 5, changing the address and data for the entire array or until the end of the
object file is reached.
Data Polling: The AT89LS51 features Data Polling to indicate the end of a byte write cycle.
During a write cycle, an attempted read of the last byte written will result in the complement of
the written data on P0.7. Once the write cycle has been completed, true data is valid on all out-
puts, and the next cycle may begin. Data Polling may begin any time after a write cycle has
been initiated.
Table 5. Status of External Pins During Idle and Power-down Modes
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data
Table 6. Lock Bit Protection Modes
Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features
2 P U U MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further
programming of the Flash memory is disabled
3 P P U Same as mode 2, but verify is also disabled
4 P P P Same as mode 3, but external execution is also disabled