Rainbow Electronics AT89LS51 - Manual (Page 11)

11
AT89LS51
3053A–8051–05/02
Oscillator
Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven, as shown in Figure 3. There are no require-
ments on the duty cycle of the external clock signal, since the input to the internal clocking
circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
Figure 2. Oscillator Connections
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 3. External Clock Drive Configuration
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special function reg-
isters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-
gram execution from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle mode is terminated by a reset, the instruction following the one that invokes
idle mode should not write to a port pin or to external memory.
Power-down
Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-
down is the last instruction executed. The on-chip RAM and Special Function Registers retain
their values until the Power-down mode is terminated. Exit from Power-down mode can be ini-
tiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or
INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not
be activated before V
CC
is restored to its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.
C2
XTAL2
GND
XTAL1
C1
XTAL2
XTAL1
GND
NC
EXTERNAL
OSCILLATOR
SIGNAL