Rainbow Electronics AT89S52 - Manual (Page 21)

AT89S52
21
Notes: 1. The signature bytes are not readable in Lock Bit Modes 3 and 4.
2. B1 = 0, B2 = 0 ---> Mode 1, no lock protection
B1 = 0, B2 = 1 ---> Mode 2, lock bit 1 activated
B1 = 1, B2 = 0 ---> Mode 3, lock bit 2 activated
B1 = 1, B1 = 1 ---> Mode 4, lock bit 3 activated
After Reset signal is high, SCK should be low for at least 64
system clocks before it goes high to clock in the enable
data bytes. No pulsing of Reset signal is necessary. SCK
should be no faster than 1/16 of the system clock at
XTAL1. For Page Read/Write, the data always starts from byte 0 to
255. After the command byte and upper address byte are
latched, each byte thereafter is treated as data until all 256
bytes are shifted in/out. Then the next instruction will be
ready to be decoded.
Table 9. Serial Programming Instruction Set
Instruction
Instruction
Format
Operation Byte 1 Byte 2 Byte 3 Byte 4
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx
0110 1001
(Output) Enable Serial Programming
while RST is high
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase Flash memory
array
Read Program Memory
(Byte Mode) 0010 0000 xxx Read data from Program
memory in the byte mode
Write Program Memory
(Byte Mode) 0100 0000 xxx Write data to Program
memory in the byte mode
Write Lock Bits (2) 1010 1100 1110 00 xxxx xxxx xxxx xxxx Write Lock bits. See Note (2).
Read Lock Bits 0010 0100 xxxx xxxx xxxx xxxx xx xx Read back current status of
the lock bits (a programmed
lock bit reads back as a ‘1’)
Read Signature Bytes (1) 0010 1000 xxx xxx xxxx Signature Byte Read Signature Byte
Read Program Memory
(Page Mode) 0011 0000 xxx Byte 0 Byte 1...
Byte 255 Read data from Program
memory in the Page Mode
(256 bytes)
Write Program Memory
(Page Mode) 0101 0000 xxx Byte 0 Byte 1...
Byte 255 Write data to Program
memory in the Page Mode
(256 bytes)
D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0
A1
2
A11 A10
A9 A8
B2 B1
A1
2
A11 A1
0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
LB3 LB2 LB
1
A5 A4 A3 A2 A1 A0
A1
2
A11 A10
A9 A8
A1
2
A11 A10
A9 A8
}
Each of the lock bits needs to be activated sequentially before
Mode 4 can be executed.