Rainbow Electronics NUC120 - Manual (Page 51)

NUC120 Series DATA SHEET
Publication Release Date: May 31, 2010
- 51 - Revision V1.02
5.17 PDMA Controller
5.17.1 Overview
The NUC120 contains a peripheral direct memory access (PDMA) controller that transfers data to and
from memory or transfer data to and from APB. The PDMA has nine channels of DMA (Peripheral-to-
Memory or Memory-to-Peripheral or Memory-to-Memory). For each PDMA channel (PDMA
CH0~CH8), there is one word buffer to do transfer buffer between the Peripherals APB IP and
Memory.
Software can stop the PDMA operation by disable PDMA [PDMACEN]. The CPU can recognize the
completion of a PDMA operation by software polling or when it receives an internal PDMA interrupt.
The NUC120 PDMA controller can increment source or destination address, fixed or wrap around
them as well.
5.17.2 Features
y AMBA AHB master/slave interface compatible, for data transfer and register read/write.
y PDMA support 32-bit source and destination addressing range address increment, fixed and
wrap around.