Rainbow Electronics MAX11645 - Manual (Page 4)

MAX11644/MAX11645
Low-Power, 1-/2-Channel, I
2
C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
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TIMING CHARACTERISTICS (Figure 1)
(V DD = 2.7V to 3.6V (MAX11645), V DD = 4.5V to 5.5V (MAX11644), V REF = 2.048V (MAX11645), V REF = 4.096V (MAX11644),
f SCL = 1.7MHz, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency f SCL 400 kHz
Bus Free Time Between a STOP (P)
and a START (S) Condition
t BUF 1.3 μs
Hold Time for START Condition t HD,STA 0.6 μs
Low Period of the SCL Clock t LOW 1.3 μs
High Period of the SCL Clock t HIGH 0.6 μs
Setup Time for a Repeated START
(Sr) Condition
t SU,STA 0.6 μs
Data Hold Time t HD,DAT (Note 11) 0 900 ns
Data Setup Time t SU,DAT 100 ns
Rise Time of Both SDA and SCL
Signals, Receiving
t R Measured from 0.3V DD - 0.7V DD 20 + 0.1C B 300 ns
Fall Time of SDA Transmitting t F Measured from 0.3V DD - 0.7V DD (Note 12) 20 + 0.1C B 300 ns
Setup Time for STOP Condition t SU,STO 0.6 μs
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t SP 50 ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C B = 400pF, Note 13)
Serial-Clock Frequency f SCLH (Note 14) 1.7 MHz
Hold Time, Repeated START
Condition
t HD,STA 160 ns
Low Period of the SCL Clock t LOW 320 ns
High Period of the SCL Clock t HIGH 120 ns
Setup Time for a Repeated START
Condition
t SU , STA 160 ns
Data Hold Time t HD , DAT (Note 11) 0 150 ns
Data Setup Time t SU , DAT 10 ns
Rise Time of SCL Signal
(Current Source Enabled)
t RCL 20 80 ns