Rainbow Electronics MAX5159 - Manual (Page 11)

The MAX5158/MAX5159’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated and the state of the registers
when exiting shutdown. The 3-bit address/control deter-
mines the following:
• registers to be updated
• clock edge on which data is to be clocked out via
the serial-data output (DOUT)
• state of the user-programmable logic output
• configuration of the device after shutdown.
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
MAX5158/MAX5159
Low-Power, Dual, 10-Bit, Voltage-Output DACs
with Serial Interface
DIN
SCLK
CS
MOSI
SCK
I/O
SPI/QSPI
PORT
SS
+5V
CPOL = 0, CPHA = 0
MAX5158
MAX5159
Figure 3. Connections for SPI/QSPI
Figure 5. Serial-Interface Timing Diagram
CS
SCLK
DIN
COMMAND
EXECUTED
9 8 16 1
C1 A0 S0 C0 D9 D8 D7 D6 D3 D2 D1 D0 S2 S1 D5 D4
______________________________________________________________________________________ 11
Figure 4. Serial-Data Format
MSB ..................................................................................LSB
16 Bits of Serial Data
Address Bits Control Bits MSB....DataBits...LSB Sub Bits
A0 C1, C0 D9.................. ......D0 S2–S0
1 Address/
2 Control Bits
10 Data Bits 000