Rainbow Electronics MAX5183 - Manual (Page 10)

MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
10 ______________________________________________________________________________________
PD
(POWER-DOWN SELECT)
DACEN
(DAC ENABLE)
POWER-DOWN MODE OUTPUT STATE
0 0 Standby
MAX5180 High-Z
MAX5183 AGND
0 1 Wake-Up Last state prior to standby mode
1 X Shutdown
MAX5180 High-Z
MAX5183 AGND
Table 1. Power-Down Mode Selection
X = Don’t care
External Reference
To disable the MAX5180/MAX5183’s internal reference,
connect REN to AV
DD . A temperature-stable, external
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150µA to drive the bias
circuit that generates the cascode current for the cur-
rent array. For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such
as the +1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower power standby mode, connect digital
inputs PD and DACEN to DGND. In standby, both the
reference and the control amplifier are active with the
current array inactive. To exit this condition, DACEN
must be pulled high with PD held at DGND. Both the
MAX5180 and MAX5183 typically require 50µs to wake
up and allow both the outputs and the reference to settle.
Shutdown Mode
For lowest power consumption, the MAX5180/MAX5183
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DAC supply current is reduced to 1µA. To enter this
mode, connect PD to DV
DD . To return to active mode,
connect PD to DGND and DACEN to DV
DD
. Table 1
lists the power-down mode selection. About 50µs are
required for the parts to leave shutdown mode and set-
tle to their outputs’ values prior to shutdown.
Timing Information
Both DAC cells in the MAX5180/MAX5183 write to their
outputs simultaneously (Figure 4). The input latch of the
first DAC (DAC1) is loaded after the clock signal transi-
tions high. When the clock signal transitions low, the
input latch of the second DAC (DAC2) is loaded.
Simultaneously at the rising edge of the next clock, the
contents of both input latches are shifted to the DAC
registers and their outputs are updated.
CLK
D0–D9
OUT1 N - 2
DAC1 DAC2 DAC1 DAC2 DAC1 DAC2
N - 1
N - 1
N - 1
N
N N N + 1 N + 1
t DS1
t CH t CL t CP
t DS2 t DH1
t DH2
OUT2 N - 2 N - 1 N
Figure 4. Timing Diagram