Rainbow Electronics MAX8668 User Manual
Page 15
MAX8667/MAX8668
1.5MHz Dual Step-Down DC-DC Converters
with Dual LDOs and Individual Enables
______________________________________________________________________________________
15
LDO Output Capacitor and Stability
Connect a 4.7µF ceramic capacitor between OUT3 and
GND, and a second 4.7µF ceramic capacitor from
OUT4 to GND. For a constant loading above 10mA, the
output capacitors can be reduced to 2.2µF. The equiv-
alent series resistance (ESR) of the LDO output capaci-
tors affects stability and output noise. Use output
capacitors with an ESR of 0.1Ω or less to ensure stable
operation and optimum transient response. Surface-
mount ceramic capacitors have very low ESR and are
commonly available. Connect these capacitors as
close as possible to the IC’s pins to minimize PCB trace
inductance.
Thermal Considerations
The maximum package power dissipation of the
MAX8667/MAX8668 is 1667mW. Make sure the power
dissipated by the MAX8667/MAX8668 does not exceed
this rating. The total IC power dissipation is the sum of
the power dissipation of the four regulators:
Estimate the OUT1 and OUT2 power dissipations as
follows:
where R
L
is the inductor’s DC resistance, and
η is the
efficiency (see the
Typical Operating Characteristics
section).
Calculate the OUT3 and OUT4 power dissipations as
follows:
The maximum junction temperature of the MAX8667/
MAX8668 is +150°C. The junction-to-case thermal
resistance (
θ
JC
) of the MAX8667/MAX8668 is 6.9°C/W.
When mounted on a single-layer PCB, the junction to
ambient thermal resistance (
θ
JA
) is about 64°C/W.
Mounted on a multilayer PCB,
θ
JA
is about 48°C/W.
Calculate the junction temperature of the
MAX8667/MAX8668 as follows:
where T
A
is the maximum ambient temperature. Make
sure the calculated value of T
J
does not exceed the
+150°C maximum.
PCB Layout
High switching frequencies and relatively large peak
currents make PCB layout a very important aspect of
design. Good design minimizes excessive EMI on the
feedback paths and voltage gradients in the ground
plane, both of which can result in instability or regula-
tion errors. Connect the input capacitors as close as
possible to the IN_ and PGND_ pins. Connect the
inductor and output capacitors as close as possible to
the IC and keep the traces short, direct, and wide.
The feedback network traces are sensitive to inductor
magnetic field interference. Route these traces away
from the inductors and noisy traces such as LX. Keep
the feedback components close to the FB_ pin.
Connect GND and PGND_ to the ground plane.
Connect the exposed paddle to the ground plane with
one or more vias to help conduct heat away from the
IC.
Refer to the MAX8668 evaluation kit for a PCB layout
example.
T
T
P
J
A
D
JA
=
+
×
θ
P
I
V
V
D
OUT
IN
OUT
4
4
34
4
=
×
−
(
)
P
I
V
V
D
OUT
IN
OUT
3
3
34
3
=
×
−
(
)
P
I
V
D
OUT
OUT
2
2
2
1
=
Ч
Ч − η
η
P
I
V
D
OUT
OUT
1
1
1
1
=
Ч
Ч − η
η
P
P
P
P
P
D
D
D
D
D
=
+
+
+
1
2
3
4