Fes6850, A.1 general information, Configuring sequence description – Acnodes FES 6850 User Manual
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All rights reserved. Product description and product specifications
are subject to change without notice. For latest product information,
please visit Acnodes’ web site at www.acnodes.com.
661 Brea Canyon Rd., Suite 3
Walnut, CA 91789
tel: 909.598.7388, fax: 909.598.0218, www.acnodes.com
FES6850
Fanless Embedded Controller comes with
Intel Celeron M 600MHz Processor
A.1 General Information
The FES-6850 utilizes ITE 8712 chipset as its watchdog timer Controller.
Below are the procedures to complete its configuration and the Acnodes intial watchdog timer
program is also attached based on which you can develop customized program to fit
your application.
Configuring Sequence Description
After the hardware reset or power-on reset, the ITE 8712 enters the normal mode with all logical
devices disabled except KBC. The initial state (enable bit ) of this logical device (KBC) is deter-
mined by the state of pin 121 (DTR1#) at the falling edge of the system reset during power-on
reset.