Xilinx PCI32 User Manual
Page 2
PCI32 Interface v3.0
2
ust 31, 2005
Product Specification v3.0.151
Fact Table Notes
1. Resource utilization depends on configuration of the interface and user design. Unused resources are trimmed by the Xilinx
technology mapper. The utilization figures reported in this table are representative of a maximum configuration.
2. Designs running at 66 MHz in devices other than Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, and Spartan-3E require one
GCLKIOB and two GCLKs. Virtex-4 implementations require additional BUFG for 200 MHz reference clock.
3. See the PCI Getting Started Guide or product release notes for current supported versions.
4. XST is a command line option only. See the PCI Getting Started Guide for details.
5. Universal card implementations require two bitstreams.
6. Virtex and Spartan-II not recommended for CardBus.
7. Commercial devices: 0
o
C < T
j
< 85
o
C.
Table 1: Core Implementation
Supported Device
Power Supply
PCI32/66
Virtex™ XCV200-FG256-6C
3.3V only
Virtex-E XCV200E-FG256-6C
3.3V only
Virtex-E XCV400E-FG676-6C
3.3V only
Virtex-4 XC4VLX25-FF668-11C/I
(6,7)
(regional clock based)
3.3V only
Virtex-4 XC4VSX35-FF668-11C/I
(6,7)
(regional clock based)
3.3V only
Virtex-4 XC4VFX20-FF672-11C/I
(6,7)
(regional clock based)
3.3V only
PCI32/33
Virtex XCV300-BG432-5C
3.3V, 5.0V only
Virtex XCV1000-FG680-5C
3.3V, 5.0V only
Virtex-E XCV100E-BG352-6C
3.3V only
Virtex-E XCV300E-BG432-6C
3.3V only
Virtex-E XCV1000E-FG680-6C
3.3V only
Virtex-II XC2V1000-FG456-4C/I/M
3.3V only
Virtex-II Pro XC2VP7-FF672-5C/I
3.3V only
Virtex-4 XC4VLX25-FF668-10C/I
(6,7)
(regional clock based)
3.3V only
Virtex-4 4 XC4VSX35-FF668-10C/I
(6,7)
(regional clock based)
3.3V only
Virtex-4 XC4VFX20-FF672-10C/I
(6,7)
(regional clock based)
3.3V only
Virtex-4 XC4VLX25-FF668-10C/I
(6,7)
(global clock based)
3.3V only
Virtex-4 XC4VSX20-FF668-10C/I
(6,7)
(global clock based)
3.3V only
Virtex-4 XC4VFX20-FF672-10C/I
(6,7)
(global clock based)
3.3V only