Texas Instruments 46 - Manual (Page 13)

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4 Expansion Options
4.1 Custom FPGA Code
4.2 Expansion Slot
4.3 Optional USB SPI Interface
Expansion Options
The EVM offers several exciting possibilities to expand the capabilities of the EVM. This allows the utmost
flexibility when prototyping an ADC circuit under conditions that mimic the end system, without the need to
develop a custom prototype board.
Using a standard JTAG interface on JP1, users have the ability to load custom logic onto the FPGA,
rapidly speeding up digital development time. This allows the flexibility of prototyping and debugging an
ADC digital interface design before developing application-specific hardware.
To take advantage of the onboard FPGA, users can download the free Xilinx WebPACK™ from the Xilinx
Web site. Select the XC3S250E-4FT256 as the FPGA and the XCF16PFSG48 as the PROM.
Note: See the Xilinx Spartan-3E Web site for complete documentation of the FPGA at:
http://direct.xilinx.com/bvdocs/publications/ds312.pdf
Schematically, the FPGA is configured in BPI mode, and it samples FPGA pins M2, M1, and M0 when the
FPGA's INIT_B is brought low. Depending of the status of M0, it boots from either the top or the bottom of
the PROM contents. The PROM allows for the storage of two FPGA bit files. In its default condition, the
EVM stores one file for ADC CMOS output at the beginning of the PROM address space and one file for
ADC LVDS output at the end of the PROM address space.
Note: When creating custom FPGA code, store any custom-developed bit files for ADC CMOS
operation in the PROM revision 0 space, and store any custom-developed FPGA code for
ADC LVDS operation in the PROM revision 1 space.
For those users who make use of a custom FPGA program on the EVM, J5 and J6 provide an
expansion-slot capability. Users can design daughtercards or breakout boards to make use of the unused
FPGA I/O pins which are brought out to the headers.
Note: The EVM provides 5 V from J14 to pin 1 of both J5 and J6. This can be used to provide
power to any designed daughtercards.
In most cases, users can use the ADC parallel interface mode to change the operational modes of the
ADC. For users requiring SPI control of the ADC, TI has developed an optional USB daughter card that
plugs into the expansion slot. With the USB daughter card, users can use a PC interface to communicate
to the ADC three-wire SPI interface, which allows for complete control of the ADC register map. Contact
the factory for this optional accessory.
SLWU028B – January 2006 – Revised November 2006 13
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