Texas Instruments DMSoC Analog to Digital Converter Interface TMS320DM36x - Manual (Page 4)

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List of Figures
1 ADC IF Block Diagram ...................................................................................................... 8
2 ADC Control (ADCTL) Register .......................................................................................... 12
3 Comparator Target Channel (CMPTGT) Register
.....................................................................
13
4 Comparison A/D Lower Data (CMPLDAT) Register ................................................................... 13
5 Comparison A/D Upper Data (CMPUDAT) Register .................................................................. 14
6 Setup Divide Value for Start A/D (SETDIV) Register
..................................................................
14
7 Analog Input Channel Select (CHSEL) Register ....................................................................... 15
8 A/D Conversion Data 0 (AD0DAT) Register ............................................................................ 15
9 A/D Conversion Data 1 (AD1DAT) Register
............................................................................
15
10 A/D Conversion Data 2 (AD2DAT) Register ............................................................................ 16
11 A/D Conversion Data 3 (AD3DAT) Register ............................................................................ 16
12 A/D Conversion Data 4 (AD4DAT) Register
............................................................................
16
13 A/D Conversion Data 5 (AD5DAT) Register ............................................................................ 17
14 Emulation Control (EMUCTRL) Register ................................................................................ 17
List of Tables
1 ADC interface Memory Map Registers .................................................................................. 11
2 ADC Control (ADCTL) Field Descriptions ............................................................................... 12
3 Comparator Target Channel (CMPTGT) Field Descriptions .......................................................... 13
4 Comparison A/D Lower Data (CMPLDAT) Field Descriptions
.......................................................
13
5 Comparison A/D Upper Data (CMPUDAT) Field Descriptions ....................................................... 14
6 Setup Divide Value for Start A/D (SETDIV) Field Descriptions ...................................................... 14
7 CHSEL setting for Channel selection .................................................................................... 15
8 Analog Input Channel Select (CHSEL) Field Descriptions
...........................................................
15
9 A/D Conversion Data 0 (AD0DAT) Field Descriptions ................................................................ 15
10 A/D Conversion Data 1 (AD1DAT) Field Descriptions ................................................................ 16
11 A/D Conversion Data 2 (AD2DAT) Field Descriptions
................................................................
16
12 A/D Conversion Data 3 (AD3DAT) Field Descriptions
................................................................
16
13 A/D Conversion Data 4 (AD4DAT) Field Descriptions ................................................................ 17
14 A/D Conversion Data 5 (AD5DAT) Field Descriptions ................................................................ 17
15 Emulation Control (EMUCTRL) Field Descriptions
....................................................................
17
List of Figures 4 SPRUFI7 – March 2009
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