Intel PXA255 - Manual (Page 150)

4-46 Intel® PXA255 Processor Developer’s Manual
System Integration Unit
4.6.5 Pulse Width Modulator Register Locations
Table 4-53 shows the registers associated with the PWM and the physical addresses used to access
them.
0x40A0_000C OSMR3 OS timer match register 3
0x40A0_0010 OSCR OS timer counter register
0x40A0_0014 OSSR OS timer status register
0x40A0_0018 OWER OS timer watchdog enable register
0x40A0_001C OIER OS timer interrupt enable register
Table 4-52. OS Timer Register Addresses (Sheet 2 of 2)
Table 4-53. Pulse Width Modulator Register Addresses
Address Name Description
0x40B0_0000 PWM_CTRL0 PWM0 Control Register
0x40B0_0004 PWM_PWDUTY0 PWM0 Duty Cycle Register
0x40B0_0008 PWM_PERVAL0 PWM0 Period Control Register
0x40C0_0000 PWM_CTRL1 PWM1 Control Register
0x40C0_0004 PWM_PWDUTY1 PWM1 Duty Cycle Register
0x40C0_0008 PWM_PERVAL1 PWM1 Period Control Register