FUJITSU F2MCTM-16LX Instruction Manuals and User Guides

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FUJITSU F2MCTM-16LX User Manual, 682 pages

Recognized languages:	English
Pages:	682
Size:	12.69 MB

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CHAPTER 1 OVERVIEW
- 1.1 Overview of MB90360
- 1.2 Block Diagram of MB90360 series
- 1.3 Package Dimensions
- 1.4 Pin Assignment
- 1.5 Pin Functions
- 1.6 Input-Output Circuits
- 1.7 Handling Device
CHAPTER 2 CPU
- 2.1 Outline of the CPU
- 2.2 Memory Space
- 2.3 Memory Map
- 2.4 Linear Addressing
- 2.5 Bank Addressing Types
- 2.6 Multi-byte Data in Memory Space
- 2.7 Registers
- 2.8 Register Bank
- 2.9 Prefix Codes
- 2.10 Interrupt Disable Instructions
- 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions
CHAPTER 3 INTERRUPTS
- 3.1 Outline of Interrupts
- 3.2 Interrupt Vector
- 3.3 Interrupt Control Registers (ICR)
- 3.4 Interrupt Flow
- 3.5 Hardware Interrupts
- 3.6 Software Interrupts
- 3.7 Extended Intelligent I/O Service (EI2OS)
  - 3.7.1 Extended Intelligent I/O Service Descriptor (ISD)
  - 3.7.2 EI2OS Status Register (ISCS)
- 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS)
- 3.9 Exceptions
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE
- 4.1 Overview of Delayed Interrupt Generation Module
- 4.2 Block Diagram of Delayed Interrupt Generation Module
- 4.3 Configuration of Delayed Interrupt Generation Module
  - 4.3.1 Delayed interrupt request generate/cancel register (DIRR)
- 4.4 Explanation of Operation of Delayed Interrupt Generation Module
- 4.5 Precautions when Using Delayed Interrupt Generation Module
- 4.6 Program Example of Delayed Interrupt Generation Module
CHAPTER 5 CLOCKS
- 5.1 Clocks
- 5.2 Block Diagram of the Clock Generation Block
  - 5.2.1 Register of Clock Generation Block
- 5.3 Clock Selection Register (CKSCR)
- 5.4 PLL/Subclock Control Register (PSCCR)
- 5.5 Clock Mode
- 5.6 Oscillation Stabilization Wait Interval
- 5.7 Connection of an Oscillator or an External Clock to the Microcontroller
CHAPTER 6 CLOCK SUPERVISOR
- 6.1 Overview of Clock Supervisor
- 6.2 Block Diagram of Clock Supervisor
- 6.3 Clock Supervisor Control Register (CSVCR)
- 6.4 Operating Mode of Clock Supervisor
CHAPTER 7 RESETS
- 7.1 Resets
- 7.2 Reset Cause and Oscillation Stabilization Wait Times
- 7.3 External Reset Pin
- 7.4 Reset Operation
- 7.5 Reset Cause Bits
- 7.6 Status of Pins in a Reset
CHAPTER 8 LOW-POWER CONSUMPTION MODE
- 8.1 Overview of Low-Power Consumption Mode
- 8.2 Block Diagram of the Low-Power Consumption Control Circuit
- 8.3 Low-Power Consumption Mode Control Register (LPMCR)
- 8.4 CPU Intermittent Operation Mode
- 8.5 Standby Mode
- 8.6 Status Change Diagram
- 8.7 Status of Pins in Standby Mode and during Hold and Reset
- 8.8 Usage Notes on Low-Power Consumption Mode
CHAPTER 9 MEMORY ACCESS MODES
- 9.1 Outline of Memory Access Modes
CHAPTER 10 I/O PORTS
- 10.1 I/O Ports
- 10.2 I/O Port Registers
CHAPTER 11 TIMEBASE TIMER
- 11.1 Overview of Timebase Timer
- 11.2 Block Diagram of Timebase Timer
- 11.3 Configuration of Timebase Timer
  - 11.3.1 Timebase timer control register (TBTC)
- 11.4 Interrupt of Timebase Timer
- 11.5 Explanation of Operations of Timebase Timer Functions
- 11.6 Precautions when Using Timebase Timer
- 11.7 Program Example of Timebase Timer
CHAPTER 12 WATCHDOG TIMER
- 12.1 Overview of Watchdog Timer
- 12.2 Configuration of Watchdog Timer
- 12.3 Watchdog Timer Registers
  - 12.3.1 Watchdog timer control register (WDTC)
- 12.4 Explanation of Operations of Watchdog Timer Functions
- 12.5 Precautions when Using Watchdog Timer
- 12.6 Program Examples of Watchdog Timer
CHAPTER 13 16-Bit I/O TIMER
- 13.1 Overview of 16-bit I/O Timer
- 13.2 Block Diagram of 16-bit I/O Timer
  - 13.2.1 Block Diagram of 16-bit Free-run Timer
  - 13.2.2 Block Diagram of Input Capture
- 13.3 Configuration of 16-bit I/O Timer
- 13.4 Interrupts of 16-bit I/O Timer
- 13.5 Explanation of Operation of 16-bit Free-run Timer
- 13.6 Explanation of Operation of Input Capture
- 13.7 Precautions when Using 16-bit I/O Timer
- 13.8 Program Example of 16-bit I/O Timer
CHAPTER 14 16-BIT RELOAD TIMER
- 14.1 Overview of the 16-bit Reload Timer
- 14.2 Block Diagram of 16-bit Reload Timer
- 14.3 Configuration of 16-bit Reload Timer
- 14.4 Interrupts of 16-bit Reload Timer
- 14.5 Explanation of Operation of 16-bit Reload Timer
  - 14.5.1 Operation in Internal Clock Mode
  - 14.5.2 Operation in Event Count Mode
- 14.6 Precautions when Using 16-bit Reload Timer
- 14.7 Sample Program of 16-bit Reload Timer
CHAPTER 15 WATCH TIMER
- 15.1 Overview of Watch Timer
- 15.2 Block Diagram of Watch Timer
- 15.3 Configuration of Watch Timer
  - 15.3.1 Watch Timer Control Register (WTC)
- 15.4 Watch Timer Interrupt
- 15.5 Explanation of Operation of Watch Timer
- 15.6 Program Example of Watch Timer
CHAPTER 16 8-/16-BIT PPG TIMER
- 16.1 Overview of 8-/16-bit PPG Timer
- 16.2 Block Diagram of 8-/16-bit PPG Timer
  - 16.2.1 Block Diagram for 8-/16-bit PPG Timer C
  - 16.2.2 Block Diagram of 8-/16-bit PPG Timer D
- 16.3 Configuration of 8-/16-bit PPG Timer
- 16.4 Interrupts of 8-/16-bit PPG Timer
- 16.5 Explanation of Operation of 8-/16-bit PPG Timer
- 16.6 Precautions when Using 8-/16-bit PPG Timer
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
- 17.1 Overview of DTP/External Interrupt
- 17.2 Block Diagram of DTP/External Interrupt
- 17.3 Configuration of DTP/External Interrupt
- 17.4 Explanation of Operation of DTP/External Interrupt
  - 17.4.1 External Interrupt Function
  - 17.4.2 DTP Function
- 17.5 Precautions when Using DTP/External Interrupt
- 17.6 Program Example of DTP/External Interrupt Function
CHAPTER 18 8-/10-BIT A/D CONVERTER
- 18.1 Overview of 8-/10-bit A/D Converter
- 18.2 Block Diagram of 8-/10-bit A/D Converter
- 18.3 Configuration of 8-/10-bit A/D Converter
- 18.4 Interrupt of 8-/10-bit A/D Converter
- 18.5 Explanation of Operation of 8-/10-bit A/D Converter
- 18.6 Precautions when Using 8-/10-bit A/D Converter
CHAPTER 19 LOW VOLTAGE DETECTION/ CPU OPERATING DETECTION RESET
- 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit
- 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit
- 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register
- 19.4 Operating of Low Voltage/CPU Operating Detection Reset Circuit
- 19.5 Notes on Using Low Voltage/CPU Operating Detection Reset Circuit
- 19.6 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit
CHAPTER 20 LIN-UART
- 20.1 Overview of LIN-UART
- 20.2 Configuration of LIN-UART
- 20.3 LIN-UART Pins
- 20.4 LIN-UART Registers
- 20.5 LIN-UART Interrupts
  - 20.5.1 Reception Interrupt Generation and Flag Set Timing
  - 20.5.2 Transmission Interrupt Generation and Flag Set Timing
- 20.6 LIN-UART Baud Rates
  - 20.6.1 Setting the Baud Rate
  - 20.6.2 Restarting the Reload Counter
- 20.7 Operation of LIN-UART
- 20.8 Notes on Using LIN-UART
CHAPTER 21 CAN CONTROLLER
- 21.1 Features of CAN Controller
- 21.2 Block Diagram of CAN Controller
- 21.3 List of Overall Control Registers
- 21.4 Classifying CAN Controller Registers
- 21.5 Transmission of CAN Controller
- 21.6 Reception of CAN Controller
- 21.7 Reception Flowchart of CAN Controller
- 21.8 How to Use CAN Controller
- 21.9 Procedure for Transmission by Message Buffer (x)
- 21.10 Procedure for Reception by Message Buffer (x)
- 21.11 Setting Configuration of Multi-level Message Buffer
- 21.12 Setting the CAN Direct Mode Register
- 21.13 Precautions when Using CAN Controller
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
- 22.1 Overview of Address Match Detection Function
- 22.2 Block Diagram of Address Match Detection Function
- 22.3 Configuration of Address Match Detection Function
  - 22.3.1 Address Detection Control Register (PACSR0/PACSR1)
  - 22.3.2 Detect Address Setting Registers (PADR0 to PADR5)
- 22.4 Explanation of Operation of Address Match Detection Function
  - 22.4.1 Example of using Address Match Detection Function
- 22.5 Program Example of Address Match Detection Function
CHAPTER 23 ROM MIRRORING MODULE
- 23.1 Overview of ROM Mirroring Function Select Module
- 23.2 ROM Mirroring Function Select Register (ROMM)
CHAPTER 24 512K-BIT FLASH MEMORY
- 24.1 Overview of 512K-bit Flash Memory
- 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory
- 24.3 Write/Erase Modes
- 24.4 Flash Memory Control Status Register (FMCS)
- 24.5 Starting the Flash Memory Automatic Algorithm
- 24.6 Confirming the Automatic Algorithm Execution State
- 24.7 Detailed Explanation of Writing to and Erasing Flash Memory
- 24.8 Notes on Using 512K-bit Flash Memory
- 24.9 Flash Security Feature
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION
- 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S)
- 25.2 Example of Serial Programming Connection (User Power Supply Used)
- 25.3 Example of Serial Programming Connection (Power Supplied from Programmer)
- 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used)
- 25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer)
CHAPTER 26 ROM SECURITY FUNCTION
- 26.1 Overview of ROM Security Function
APPENDIX
- APPENDIX A I/O Maps
- APPENDIX B Instructions
- APPENDIX C Timing Diagrams in Flash Memory Mode
- APPENDIX D List of Interrupt Vectors

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