Rainbow Electronics DS2165Q - Manual (Page 4)

DS2165/DS2165Q
041295 4/17
DS2165 BLOCK DIAGRAM Figure 1
X SIDE PCM/ADPCM
DATA INTERFACE
SERIAL PORT CONTROL/
HARDWARE MODE LOGIC
Y SIDE PCM/ADPCM
DATA INTERFACE
RESET AND TEST LOGIC
ADPCM
PROCESSING
ENGINE
MCLK
V DD
V
SS
FSX
CLKX
XIN
XOUT
SCLK
SPS
CS
SDI
A0 - A5
FSY
CLKY
YIN
YOUT
RST
TM0
TM1
SERIAL PORT WRITE Figure 2
ЙЙ
ЙЙ
ЙЙ
ЙЙ
ЙЙ
ЙЙ
A0 A1 A2 A3 A4 A5 X/Y 0 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7
ADDRESS/COMMAND CONTROL
NOTE:
1. A 2-byte write is shown.
The bypass feature is enabled when BYP is set and IPD
is cleared. During bypass, no expansion or compres-
sion occurs. Bypass operates on bytewide (8 bits) slots
when CP/EX is set and on nibble-wide (4 bits) slots
when CP/EX is cleared. A-law (U/A = 0) and
µ
-law (U/A = 1) PCM coding is inde-
pendently selected for the X and Y channels via CR.2. If
BYP and IPD are cleared, then CP/EX determines if the
input data is to be compressed or expanded.