Xilinx MIcroblaze Development Spartan-3E 1600E - Manual (Page 86)

84 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
www.xilinx.com UG257 (v1.1) December 5, 2007
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM R
x Stores MicroBlaze processor code in the StrataFlash device and shadows the code into
the DDR memory before executing the code.
x Stores non-volatile data from the FPGA.
StrataFlash Connections
Table 11-1 shows the connections between the FPGA and the StrataFlash device.
Although the XC1600E FPGA only requires just slightly under 6 Mbits per configuration
image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit
StrataFlash. The MicroBlaze Development Kit board ships with a 128 Mbit device. Address
line SF_A24 is not used.
In general, the StrataFlash device connects to the XC1600E to support Byte Peripheral
Interface (BPI) configuration. The upper four address bits from the FPGA, A[23:19] do not
connect directly to the StrataFlash device. Instead, the XC2C64 CPLD controls the pins
during configuration. As described in Table 11-1 and Shared Connections , some of the
StrataFlash connections are shared with other components on the board.