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Motorola MVME2400 User Manual

Page 65

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Block Diagram

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3-17

3

Notes

1. SDRAM speed attributes are programmed for the
following: CAS_latency = 2, tRCD = 2 CLK Periods, tRP =
2 CLK Periods, tRAS = 5 CLK Periods, tRC = 7 CLK
Periods, tDP = 2 CLK Periods, and the swr_dpl bit is set in
the SDRAM Speed Attributes Register.

2. The Hawk is configured for “no external registers” on the
SDRAM control signals.

3. tB1, tB2, tB3, and tB4 are specified in the following figure.

Figure 3-2. Timing Definitions for PPC Bus to SDRAM Access

tB1(From Idle)

tB1(Back-to-Back)

tB2

tB3

tB4