Sundance SMT395Q - Manual (Page 13)

Version 1.0.7 Page 13 of 31 SMT395Q User Manual
FPGA resources
Interrupts
See SMT6400 help file.
DDR SDRAM
The FPGA is directly connected to a 256MB memory bank. This interfaces via a 64-
bit data bus.
Full details on the DDR memory interface can be viewed on the
Xilinx web site ; and
an application note can be downloaded from here ;
SDB
The SMT395Q provides two SHB which are 32-bit SDB.
They are numbered SDB_0 for SHB_A, SDB_1 for SHB_B.
See SMT6400 help file.
SDB Clock selection
The SDB clock selection is not implemented. The clock is running at the EMIF speed i.e.
120MHz.
RSL
The standard RSL speed is 2.5Gbps.
A -6 speed grade FPGA is required for speeds above 2Gbps.
The SMT395Q module includes a 125MHz differential oscillator (EG-2121CA LV-PECL) for
the 2.5Gbps speed.
Global bus
The SMT395Q provides one global bus interface.
See SMT6400 help file.