Foxconn A85GM - Manual (Page 39)

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■ DCT channels A and B can be ganged as a single logical 128-bit DIMM.
■ Offers highest DDR2 bandwidth.
■ Requires both DIMMs in a logical pair to have identical size and timing parameters, both
DCTs programmed identically.
Unganged channels
■ DCT channels A and B operate as two completely independent 64-bit channels (both chan-
nels operate at the same frequency).
■ Reduce DRAM page conflicts – more concurrent open dram pages .
■ Better bus efficiency.
Burst lengths supported
When both DCTs are enabled in unganged mode, BIOS must initialize the frequency of each
DCT in order.
DRAM Timing Configuration
CMOS Setup Utility - Copyright (C) 1985-2006, American Megatrends, Inc.
DRAM Timing Configuration
DRAM Timing Configuration Help Item
DRAM Timing Mode [Auto]
Auto
DCT 0
↑↓←→:Move Enter:Select +/-/:Value F10:Save ESC:Exit
F1:General Help F9:Optimized Defaults
[Auto]
Options
► DRAM Timing Mode
When both DCTs (DRAM controller) are enabled in unganged mode, BIOS must initialize the
frequency of each DCT in order, you also can configure the timings manually.
Settings are: [Auto], [DCT 0]. (appear in AM2 CPU)
Settings are: [Auto], [DCT 0], [DCT 1], [Both]. (appear in AM2+/AM3 CPU)
► CAS Latency
The number of memory clocks it takes a DRAM to return data after the read CAS_L is asserted
depends on the memory clock frequency. The value that BIOS programs into the memory
controller is a function of the target clock frequency. The target clock frequency is determined
from the supported CAS latencies at given clock frequencies of each DIMM.
► TRCD (RAS-to-CAS Delay)
This item allows you to select a delay time (in clock cycles) between the CAS# and RAS#
strobe signals.
► TRP (Precharge Command Period)