CyClone Microsystems FEP Blade Intelligent I/O Controller COMPACTPCI-824 - Manual (Page 18)

HARDWARE
2-8 CPCI-824 User’s Manual
Revision 1.0, January 2006
Table 2-6. Breeze Start-up LEDS
2.8.4 Geographic Addressing
CompactPCI backplanes that support 64-bit connector pin assignments are required to provide a unique
differentiation based upon which physical slot the board has been inserted. The CPCI-824 makes this
definition available to the software. The definition for GA[4:0] is shown in Figure 2.3.
Figure 2-3. Geographic Addressing Register, E800 0001h
LED TESTS
ACT TLBs set. External bus controller set
ST0 PCB arbitration priorities set
ST1 Interrupt controller set
IOP UART set
ACT, ST0 System reset check done.
ACT, ST1 I2C bus set. (first pass)
ACT, IOP Board configuration initialized
ST0, ST1 Board strapping validated
ST0, IOP I2C bus set. (second pass)
ST1, IP SDRAM initialized
ACT, ST0, ST1 SDRAM checked and cleared.
None Breeze entry
7 6 4 5 3 2 1 0
GA0
GA4
GA3
GA2
GA1
READ O nly
(1) +5V
(0) G ND