C.7 i, Nterrupt status register, Base+20h – Advantech PC-LabCard PCI-1784 User Manual
Page 42: C.7 interrupt status register — base+20h
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C.7 Interrupt status register — BASE+20H
Table C-6 PCI-1784 Register for interrupt status
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Base Addr.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Interrupt status
DI3
DI2
DI1
DI0
IX3
IX2
IX1
IX0
UN3
UN2
UN1
UN0
OV3
OV2
OV1
OV0
20H
R
IF
TM
UC3
UC2
UC1
UC0
OC3
OC2
OC1
OC0
OVn
Counter overflow interrupt flag (n: 0 ~ 3)
0
Disable
1
Enable
UNn
Counter underflow interrupt flag (n: 0 ~ 3)
0
Disable
1
Enable
IXn
Index input interrupt flag (n: 0 ~ 3)
0
Disable
1
Enable
DIn
Digital input interrupt flag (n: 0 ~ 3)
0
Disable
1
Enable
OCn
Counter over compare interrupt by flag (n: 0 ~ 3)
0
Disable
1
Enable
UCn
Counter under compare interrupt flag (n: 0 ~ 3)
0
Disable
1
Enable
TM
Timer pulse interrupt flag
0
Disable
1
Enable
IF
Overall interrupt enable flag
0
Disable
1
Enable