IEI Integration PXE-19S2 - Manual (Page 2)

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6. PWRGD: External Power Good Connector
7. SM-BUS: External System Management BUS Connector
8. CN1: PCIE X16 SDVO Control Signal Pin
9. J1, J2, J3: Write Protect Setup
J1
¨
J2 and J3 are the EEPROM write protect pin of the PCI Express to
PCI Bridge will allow EEPROM normal read/write operations when J1
¨
J2 or J3 held high. When the Jump is brought low and the EEPROM
WPEN bit is “1”, all write operations to the status register are inhibited.
10. J4
© © © ©
J5
© © © ©
J6 : PCI Slot Freq. Setting
1 2
¡
J4
© © © ©
J5
© © © ©
J6
DESCRIPTION
ON (Short) 33MHz
OFF (Open) Auto (default)
1 2
¡
2
1
¡
PIN DESCRIPTION
1 GND
2 PWRGD
2
1
¡
PIN DESCRIPTION
1 SMDATA
2 SMBCLK
1 2 3
¡
PIN DESCRIPTION
1 EXP_EN
2 SDVO_CLK
3 SDVO_DAT
J1
© © © ©
J2
© © © ©
J3
DESCRIPTION
ON (Short) Write Inhibited
OFF (Open)
Normal Read/Write
(default)