Asus P4BGL-MX - Manual (Page 46)

2-16 Chapter 2: BIOS Information
2.4.1 Chip Configuration
SDRAM CAS Latency [2T]
This item controls the latency between the SDRAM read command and
the time the data actually becomes available.
SDRAM RAS to CAS Delay [3T]
This item controls the latency between the DDR SDRAM active command
and the read/write command.
SDRAM RAS Precharge Delay [3T]
This item controls the idle clocks after issuing a precharge command to
the DDR SDRAM.
SDRAM Active Precharge Delay [5T]
This item controls the number of DDR SDRAM clocks used for DDR
SDRAM parameters.
SDRAM Idle Timer [Infinite]
Configuration Options: [Infinite] [0T] [8T] [16T] [64T] [Auto]
Onboard VGA Memory Size [8MB]
This field allows you to set the size of shared memory for internal VGA.
SDRAM Configuration [By SPD]
This parameter allows you to set the optimal timings for items 2–5,
depending on the memory modules that you are using. The default setting
is [By SPD], which configures items 2–5 by reading the contents in the
SPD (Serial Presence Detect) device. The EEPROM on the memory
module stores critical information about the module, such as memory type,
size, speed, voltage interface, and module banks.
Configuration options: [User Defined] [By SPD]
The SDRAM parameters (items 2~5) become configurable only when
you set the SDRAM Configuration to [User Defined].