AAEON AEC-6523 - Manual (Page 78)

E m b e d d e d C o n t r o l l e r A E C - 6 5 2 3
Appendix A Programming the Watchdog Timer A-2
A.1 Programming
AEC-6523 utilizes the ITE 8783 chipset as its watchdog timer
controller. Below are the procedures to complete its configuration
and the AAEON initial watchdog timer program is also attached
based on which you can develop customized program to fit your
application.
Configuring Sequence Description
After the hardware reset or power-on reset, the ITE 8783 enters the
normal mode with all logical devices disabled except
KBC. The initial state (enable bit ) of this logical device (KBC) is
determined by the state of pin 121 (DTR1#) at the falling edge of
the system reset during power-on reset.
There are three steps to complete the configuration setup: (1) Enter
the MB PnP Mode; (2) Modify the data of configuration registers; (3)