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Timing diagram: spi write data transfer figure 12 – Rainbow Electronics DS1722 User Manual

Page 12

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DS1722

12 of 13

TIMING DIAGRAM: SPI WRITE DATA TRANSFER Figure 12

*SCLK can be either polarity, timing shown for CPOL = 1.

NOTES:

1. All voltages are referenced to ground.

2. Logic 0 voltages are specified at a sink current of 4 mA.

3. Logic 1 voltages are specified at a source current of 1 mA.

4. I

CC

specified with SCLK=V

DDD

and CE=GND. Typical I

CC1

is 0.25 µA and I

CC

is 0.3 mA at 25°C

and V

DDD =

2.65V

.

5. Measured at V

IH

=0.7 V

DDD

or V

IL

=0.2 V

DDD

and 10 ms maximum rise and fall time.

6. Measured with 50 pF load

7. Measured at V

OH

=0.7 V

DDD

or V

OL

=0.2 V

DDD

. Measured from the 50% point of SCLK to the V

OH

minimum of SDO.

8. Figure 13 shows mean thermometer error for a pre-characterization sample. Data covering a larger

sample over the full temperature range is pending.