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At90so4, Part number, Description – Rainbow Electronics AT90SO4 User Manual

Page 2: High-speed spi controller

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AT90SO4

6579A–SMS–29Jan10

Part Number

AT

: Atmel

90

: AVR Core

SO

: Smart Object

4

: EEPROM Size

xxx

: Chip Personalization Number*

P

= Z : DFN8 Package

R : SOIC8 Package

* For more details about the Chip Personalization Number, please contact your local ATMEL sales office.

Description

Targeted for low cost security applications, the AT90SO4 is based on the secureAVR architecture that allows the linear addressing of up
to 8M bytes of code and up to 16M bytes of data as well as a number of new functional and security features. It is a low-power, high-per-
formance, 8/16-bit microcontroller with ROM program memory, EEPROM data memory based on the secureAVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90SO4 achieves throughputs close to 1 MIPS per MHz. Its
Harvard architecture includes 32 general purpose working registers directly connected to the ALU, allowing two independent registers to
be accessed in one single instruction executed in one clock cycle.

The ability to map the EEPROM in the code space allows parts of the program memory to be reprogrammed in-system. This technology
combined with the versatile 8/16-bit CPU on a monolithic chip provides a highly flexible and cost-effective solution to many embedded
security applications.

Additional security features include power and frequency protection logic, logical scrambling on program data and addresses, Power
Analysis countermeasures and memory accesses controlled by a supervisor mode. A block diagram of the AT90SO4 is shown in Figure
1 hereafter

.

High-Speed SPI Controller

The AT90SO4 hosts a High Speed SPI interface for full-duplex and synchronous data transfer. When configured as a master, the control-
ler provides clock up to 20MHz thanks to the dedicated internal VFO clock system.

A specific DMA contoller allows fast tranfers between DPRAM banks to CPU RAM. The internal DPRAM memory provides 4 DPRAM
buffers of 16 bytes each: 2 for Reception and 2 for Transmission.

The SPI controller features three sources of interrupt (Byte Transmitted, Time-out and Reception Overflow) and a programmable clock
and inter-bytes (guardtime) delays.

AT90SO4-xxx-P