Rainbow Electronics DS1990A - Manual (Page 6)

DS1990A
6 of 10
1-WIRE SIGNALING
The DS1990A requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data.
All these signals except presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS1990A is shown in Figure 5.
A Reset Pulse followed by a Presence Pulse indicates the DS1990A is ready to send or receive data given
the correct ROM command.
The bus master transmits (T
X
) a reset pulse ( a low signal for a minimum of 480
µ
s). The bus master then
releases the line and goes into receive mode (R
X
). The 1-Wire bus is pulled to a high state via the
5 k
Ω
pullup resistor. After detecting the rising edge on the data contact, the DS1990A waits (t
PDH
, 15-60
µ
s) and then transmits the presence pulse (t
PDL
, 60-240
µ
s).
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS1990A to the
master by triggering a delay circuit in the DS1990A. During write time slots, the delay circuit determines
when the DS1990A will sample the data line. For a read data time slot, if a “0” is to be transmitted, the
delay circuit determines how long the DS1990A will hold the data line low overriding the 1 generated by
the master. If the data bit is a “1”, the iButton will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5
480
µ
s
≤
t
RSTL
<
∞
*
480
µ
s
≤
t
RSTH
<
∞
(includes recovery time)
15
µ
s
≤
t
PDH
< 60
µ
s
60
µ
s
≤
t
PDL
< 240
µ
s
∗
In order not to mask interrupt signaling by other devices on the 1-Wire bus, t
RSTL
+ t
R
should always
be less than 960
µ
s.
RESISTOR
MASTER
DS1990A