Rainbow Electronics APC5830 - Manual (Page 9)

APLUS INTEGRATED CIRCUITS INC.
APC5830
www.aplusinc.com.tw TEL : 886-2-2782-9266 9
z 3FF4 : B
ANK REGISTER FOR
CPU. W
RITE ONLY
.
z 3FF5 : B ANK REGISTER MSB BIT FOR CPU. W RITE ONLY .
B
ANK REGISTER IS
9
BITS REGISTER
($3FF5
BIT
0, $3FF4
BIT
7-0).
T
HE MEMORY RANGE OF BANK IS FROM
$4000
TO
$7FFF.
B
IT
1: R
ESERVED
.
B IT 2: = 1 V OICE 0 BUFFER BE TRANSFERRED TO DAC PORT DIRECTLY .( DEFAULT )
= 0 V OICE 0 BUFFER WILL BE TRANSFERRED TO DAC PORT WHEN TIMER _ B NMI HAPPEN .
B IT 7-3 : R ESERVED .
z 3FF6 : P ORT _ C [7..0] DATA REGISTER . R EAD AND WRITE .
z 3FF7 : P
ORT
_
C
[15..8]
DATA REGISTER
. R
EAD AND WRITE
.
z 3FF8: P
ORT
_
C
[7..0]
DIRECTION REGISTER
. W
RITE ONLY
.
A N ‘1’ IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT _ C TO BE OUTPUT .
T
HE DEFAULT VALUE FOR EACH BIT IS ZERO
.
z 3FF9: P
ORT
_
C
[15..8]
DIRECTION REGISTER
. W
RITE ONLY
.
A
N
‘1’
IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT
_
C TO BE OUTPUT
.
T
HE DEFAULT VALUE FOR EACH BIT IS ZERO
.
z 3FFA :ADC
REGISTER
. R
EAD ONLY
.
W
HEN THE TIMER B
NMI
OCCURS
,
THE
A/D
CONVERSION PROCESS STARTS AND THE
S/H
CIRCUIT STOP SAMPLING AND BEGIN HOLDING IT UNTIL THE
ADC
PROCESS IS FINISHED
.
T
HE
ADC
INT WILL GENERATE WHEN
ADC
PROCESS IS FINISHED
.
z 3FFB,3FFC :….
NO USE
z 3FFD : ……
NO USE
z 3FFE: V
OICE CHANNEL
1
LOW BYTE AND SYSTEM CONTROL
3. W
RITE ONLY
.
3FFE 0 1
BIT - 0
S
EPARATE MODE FOR
DAC
OUTPUT
(
DEFAULT
)
M IX MODE FOR DAC OUTPUT .
BIT - 1
S EPARATE MODE FOR PWM
OUTPUT ( DEFAULT )
M
IX MODE FOR
PWM
OUTPUT
BIT - 2
NO USE
(
MUST
0)
BIT - 3 NO USE ( MUST 0)
BIT – 7 ~ 4 VOICE CHANNEL 1 LOW NIBBLE BYTE .