Rainbow Electronics T89C51RC2 - Manual

Rev. A – 31-May-01
1
This errata sheet describes the functional deviations known at the release date of this
document.
Errata History
Trouble descriptions
Lot Number Trouble list Status
All
T01, T02, T03, T04, T05, T06, T07, T08, T09, T10, T11,
T12, T13
Not Fixed
T01 During UART reception, clearing REN may generate unexpected IT.
Description During Uart reception, if the REN bit is cleared between a start bit detection and the
end of reception, the Uart will not discard the data (RI is set).
Workaround Test REN at the beginning of Interrupt routine just after CLR RI, and to run the
Interrupt routine code only if REN is set.
T02 Double IT on external falling edge on INT1 or INT0 in X2 Mode
Description When CPU is in X2 mode and Timer1 or Timer 0 in X1 mode (CKCON = 0x7F), IEx
flag is not cleared by hardware after servicing interrupt. In this case, the CPU
executes the ISR a second time.
Workaround The work around is to clear IEx bit in Interrupt subroutine.
INT1_ISR : ; Interrupt sub routine
CLR IE1
....
T03 Internal Resistor on Reset Pin
Description Deviation from electrical specification. Typical value for internal resistor on Reset pin:
20K Ohms
Workaround No
80C51 MCUs
T89C51RB2
T89C51RC2
Errata Sheet