NXP Semiconductors ISP1563 - Manual (Page 4)

NXP Semiconductors
AN10050
Designing a Hi-Speed USB host PCI adapter using ISP1562/63
AN10050_4 © NXP B.V. 2007. All rights reserved.
Application note Rev. 04 — 1 November 2007 4 of 18
3. Register HcRhStatus = 18000h. This implies that bit LPSC = 1b (port powered).
Microsoft Windows 2000, Windows XP and Linux drivers normally use this sequence.
The order of the steps may, however, be reversed in Windows CE default drivers so
changes are required for normal functionality.
3. Description of the application schematics
The schematics (see Section 5 ) contain a complete implementation of the ISP1562/3 and
allow testing of all its features in different types of design: PCI add-on card, onboard
design in standard desktop or mobile solution.
In the case of a standard PCI add-on card design, some simplifications to the schematics
can be done, as described here. Some features will not be normally used in a standard
PCI add-on card. For example: The legacy support, wake-up from S3
cold
(no external
+5 V input for V
BUS
) and the alternative 48 MHz clock input. All these alternatives,
however, are included in the schematics and are described in this document.
3.1 Distribution of power sources and power management support
As shown in the schematics (see Section 5 ), a simple solution by using one jumper (JP1)
may be adopted to choose between PCI V
CC
= 3.3 V or PCI V
AUX
= 3.3 V as the main
power source for the ISP1562/3. Power source PCI V
AUX
= 3.3 V is introduced in PCI
Local Bus Specification Revision 2.2. It allows powering an add-on card and generation
of the PME# signal, even if the system is in a deep power management state and PCI
V
CC
is off. An alternative solution to using a jumper may be a simple circuit containing a
pair of MOSFET transistors that allows to detect the presence of PCI V
AUX
= 3.3 V and
automatic selection of the input voltage.
Selection of PCI V
CC
= +3.3 V must be the default position of jumper JP1 in the case of a
standard add-on card design. The other possible position of JP1 selects PCI V
AUX
= 3.3 V
for complete Power Management tests, including S3
cold
in the case of on-motherboard or
notebook. Note that pins 3, 77, 98 and 100 of the ISP1562, and pins 6, 12 and 95 of the
ISP1563 are connected to the PCB V
CC(I/O)_AUX
power plane and pins 86 and 93 of the
ISP1562, and pins 104, 111, 120 and 128 of the ISP1563 are connected to the PCB
V
DDA_AUX
power plane. Each of these planes is separated from PCI V
AUX
by its own set of
inductors and decoupling capacitors.
Although most of the motherboards provide the PCI V
AUX
power source in all system
power management modes, including S3
cold
, the PCI +5 V power supply is
simultaneously interrupted with PCI V
CC
= +3.3 V.
In certain standby modes (S3
cold
), the devices connected to USB ports will not be
powered once the +5 V power is removed because the V
BUS
voltage present on USB
connectors is normally derived from the PCI +5 V power supply. Therefore, PCI V
AUX
is
not useful in the case of a standard PCI add-on card implementation for a system wake-
up from S3
cold
. It is, however, a very useful feature for onboard and mobile application
designs because it allows additional considerable power savings and also wakes up the
system by using a USB device. The system wake-up from S3
cold
, generated from a USB
device, for example, USB mouse or USB keyboard, connected to the ISP1562/3 host
controller must be supported in system’s BIOS, hardware (a continuous +5 V must be
supplied to V
BUS
) and operating system drivers.
To be able to test the remote wake-up, especially, from those power management states
in which the +5 V power source on PCI is not present, for example, S3
cold
, a special
connector (J1) is added for an external +5 V source. Any external independent power