Intel PXA255 - Manual (Page 541)

Intel® PXA255 Processor Developer’s Manual 16-1
Network SSP Serial Port
16
This chapter describes the signal definitions and operation of the Intel® PXA255 Processor
Network Synchronous Serial Protocol (NSSP) serial port.
The NSSP is configured differently than the SSPC.
16.1 Overview
The NSSP is a synchronous serial interface that connects to a variety of external analog-to-digital
(A/D) converters, telecommunication CODECs, and many other devices that use serial protocols
for data transfer. The NSSP provides support for the following protocols:
• Texas Instruments (TI) Synchronous Serial Protocol*
• Motorola Serial Peripheral Interface* (SPI) protocol
• National Semiconductor Microwire*
• Programmable Serial Protocol (PSP)
The NSSP operates as full-duplex devices for the TI Synchronous Serial Protocol*, SPI*, and PSP
protocols and as half-duplex devices for the Microwire* protocol.
The FIFOs can be loaded or emptied by the CPU using programmed I/O or DMA burst transfers.
16.2 Features
• Supports the TI Synchronous Serial Protocol*, the Motorola SPI* protocol, National
Semiconductor Microwire*, and a Programmable Serial Protocol (PSP)
• Two independent transmit and receive FIFOs, each 16 samples deep by 32-bits wide
• Sample sizes from four to 32-bits
• Maximum bit rate of 13 Mbps in slave of clock mode, requires using DMA
• Master-mode and slave-mode operation
• Receive-without-transmit operation