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5 register descriptions, 1 receive buffer register (rbr), 2 transmit holding register (thr) – Intel PXA255 User Manual

Page 580: 3 divisor latch registers (dll and dlh), Rbr bit definitions -10, Thr bit definitions -10, Section 17.5.3

5 register descriptions, 1 receive buffer register (rbr), 2 transmit holding register (thr) | 3 divisor latch registers (dll and dlh), Rbr bit definitions -10, Thr bit definitions -10, Section 17.5.3 | Intel PXA255 User Manual | Page 580 / 598 5 register descriptions, 1 receive buffer register (rbr), 2 transmit holding register (thr) | 3 divisor latch registers (dll and dlh), Rbr bit definitions -10, Thr bit definitions -10, Section 17.5.3 | Intel PXA255 User Manual | Page 580 / 598
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