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11 udc status/interrupt register 0 (usir0), 1 endpoint 0 interrupt request (ir0), 2 endpoint 1 interrupt request (ir1) – Intel PXA255 User Manual
Page 439: 11 udc status/interrupt register 0 (usir0) -39, Usir0 bit definitions -39
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11 udc status/interrupt register 0 (usir0), 1 endpoint 0 interrupt request (ir0), 2 endpoint 1 interrupt request (ir1) | 11 udc status/interrupt register 0 (usir0) -39, Usir0 bit definitions -39 | Intel PXA255 User Manual | Page 439 / 598
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See also other documents in the category Intel Acoustics:
PXA255
(600 pages)
Fireface 800
(95 pages)