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1 passive display timing, 2 active display timing, 3 pixel data pins (l_ddx) – Intel PXA255 User Manual

Page 271: 6 dma, Dma -9

1 passive display timing, 2 active display timing, 3 pixel data pins (l_ddx) | 6 dma, Dma -9 | Intel PXA255 User Manual | Page 271 / 598 1 passive display timing, 2 active display timing, 3 pixel data pins (l_ddx) | 6 dma, Dma -9 | Intel PXA255 User Manual | Page 271 / 598
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