TABLE OF FIGURES
Figure 1: Block Diagram .............................................................................................................................11
Figure 2: CPLD state machine.....................................................................................................................14
Figure 3: FPGA connections to Bank1 of QDRII .......................................................................................15
Figure 4: Clocking distribution diagram .....................................................................................................19
Figure 5: Top View......................................................................................................................................23
Figure 6: Bottom View ................................................................................................................................24
Figure 7: JTAG connector Top View ..........................................................................................................29
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
Page 5 of 34
