Sensoray 826 - Manual (Page 35)

Preload Behavior
Mode Register
B P bit
Preload Trigger Type
Counter Core
Loads From
Activated
After Preload
0 Any Preload0 Preload0
1
Zero Counts Reached Active preload Alternate preload
Any except Zero Counts Reached Preload0 Preload1
Preload triggers are prioritized. If two simultaneous preload triggers occur, the one with the highest priority is considered to
be the cause of the preload and the preload mechanism will behave accordingly.
Some types of preload triggers are enabled and disabled by ExtIn when ExtIn is configured as a preload permissive (see
“ExtIn Signal”). These triggers are disabled when ExtIn is negated and enabled with ExtIn is asserted.
Preload Trigger Type Priority
Enabled/Disabled by ExtIn (when ExtIn
is configured as preload permissive)
Channel switched to running state 7 (highest) No
Zero counts reached 6 No
Compare1 match 5 Yes
Compare0 match 4 Yes
Index rising edge 3 Yes
Index falling edge 2 Yes
Index active level 1 Yes
Soft preload 0 (lowest) Yes
7.1.7 Tick Generator
Each counter channel has an independent tick generator that can be used to create counting gates; this is useful for
frequency measuring applications. The generator can produce periodic pulses at intervals ranging from one microsecond to
ten seconds in decade steps. The channel's external IX input or the ExtOut output from any counter channel can be used in
lieu of the internal tick generator if a custom gate time is needed.
7.1.8 Cascading
Limited cascading of counter channels is supported. Each channel receives overflow and underflow signals from the
adjacent lower channel (channel 0 receives from channel 5). A channel may be cascaded onto the adjacent lower channel by
setting K=4 in its mode register (see S826_CounterModeWrite). Note that when two channels are cascaded, only the count
function is extended; the snapshot and preload mechanisms will continue to operate independently. Each cascade is limited
to two counters.
7.1.9 Status LEDs
Each counter channel is associated with a status LED that indicates clock pulses are detected on that channel. The LED
flashes at a constant rate while the clock signal is toggling. The LEDs are labeled E0-E5, corresponding to counter channels
0-5 respectively.
7.1.10 Reset State
Upon board reset, all counter channels are set to the “halted” state (see S826_CounterStateWrite for details). In addition, a
board reset will also zero the Mode, Preload, and Compare registers.
826 Instruction Manual 30 Counters