Rainbow Electronics DS3170 - Manual (Page 223)

DS3170 DS3/E3 Single-Chip Transceiver
223 of 233
Figure 17-7. SPI Interface Timing Diagram
NOTE:
1. Clock edge reference to data controlled by CPHA and CPOL settings.
Refer to functional timing diagrams.
2. Not defined, but usually MSB of character just received.
CS
INPUT
SPI_SCLK
SPI_SCLK 1
MOSI
INPUT
MISO
OUTPUT
MSB
BITS
13 - 0
SLAVE
MSB
BITS 6-1 NOTE 2
BIT 14
t1
t4 t5
t2
t3
SLAVE
LSB
t8
t6 t7
t9 t10