Rainbow Electronics DS26504 - Manual (Page 13)

DS26504 T1/E1/J1/64KCC BITS Element
13 of 128
Figure 3-4. Master Clock PLL Diagram
PRE-SCALER
DIVIDE BY 1, 2, 4,
OR 8
MCLK PIN
2.048MHz to
1.544MHz PLL
w/ bypass
JA CLOCK
TO CLOCK AND DATA
RECOVERY ENGINE IN
RECEIVE LIU
X12,X16
MULTIPLER
PLL
LIC2.3
(JACKS0)
LIC4.6
(MPS0)
LIC4.7
(MPS1)
12.8MHz to
2.048MHz PLL
w/ bypass
LIC2.7
(JACKS1)
(HARDWARE MODE)